1. Field of the Invention
The present invention relates to computer systems. More particularly, the present invention relates to a software/hardware interface of a computer system for automatically initiating a predetermined operating mode in response to a signal.
2. Description of the Related Art
A processor operating in a PC/AT computer architecture may operate in various functional modes. One mode of operation is an 80.times.86 real mode in which memory is addressed using a segment value that is multiplied by 16 and added to an offset value to generate a physical memory address. In the real mode no access checks are made to verify that the processor is addressing a correct code, data segment and I/O address space, thereby improving performance but limiting system robustness and security since illegal codes and addresses are not detected by hardware. FIG. 1 illustrates a memory map of a processor address space 100 including a conventional disk operating system (DOS) 104 with a first 640 kbytes that are reserved for the operating system and application programs. Above the first 640 kbytes are stored a video RAM and various optional Basic Input/Output System (BIOS) extensions 108. Extended memory 110 begins above 1 Mbyte and may extend to 4 gigabytes. Memory addresses in the range of A0000h and FFFFFh are commonly referred to as "Upper Memory Blocks" (UMB) 106. The UMB is a highly overused resource when the computer executes in the 80.times.86 real mode since system memory addressability is limited to 1 MB. For example, various resources that typically reside in the UMB include:
ROM modules which are located on ISA adapter cards PA1 Ethernet transmit/receive buffers PA1 System BIOS in E0000 and F0000 segments PA1 VGA BIOS from C0000-C8000 PA1 Flash or ROM Disks in embedded applications, and PA1 DOS extenders which use V8086 mode to page DRAM from above 1 MB into the UMB for use by DOS and applications.
The DOS memory configuration is a relic of the limited memory address space of early generation microprocessors. Subsequent computer systems and architectures have conformed to the memory configuration limitations in varying degrees. Resource conflicts have been common and still frequently occur in attempting to conform architectures with multiple peripheral devices to antiquated memory configurations. Some computer system architectures, for example an ElanSC400 architecture, increase the demand for memory address space in the Upper Memory Blocks by allowing new memory-mapped resources, such as a PCMCIA (Personal Computer Memory Card International Association) and MMS (Memory Management System) windowing hardware, to be mapped into the Upper Memory Blocks.
System Management Mode (SMM) is a feature of computer systems such as the Enhanced AM486 CPU Core, manufactured by Advanced Micro Devices, Santa Clara, Calif. SMM is often used to support system-level power management. Under certain circumstances, the system's power management driver may shut power off to selected system peripherals. When operating system or application software subsequently performs an I/O access to the powered down device, an SMI may be generated which places the system into SMM. Inside of SMM, the SMI handler can turn the power back on to the required peripheral(s), and reconfigure the peripherals to a pre-powered down state. When SMM is exited, the I/O instruction may be restarted automatically by the CPU and the I/O access will occur transparently as if the power had never been shut off to the peripheral device in the first place. The System Management Mode is typically activated by an external signal to a dedicated terminal that generates an interrupt, specifically a System Management Interrupt (SMI), and redirects execution by directing addressing of executable program code to an SMI handler which resides in SMM RAM. The System Management Mode supports a technique that is application software transparent for taking control of the processor to handle selected system-related events. To achieve a control shift that is transparent to application software, the System Management Mode must save the state of the CPU, handle the SMM event, then restore the CPU state to the condition prior to the SMI. Optimally, the SMM handler should reside in memory (SMRAM) that is not normally accessible to either the operating system (O/S) or any application program. A failure to allocate the SMM handler to restricted memory raises the constraint that the SMRAM address must be known to the O/S or application and usage at the address avoided so that the memory region is not inadvertently allocate to O/S or application usage. The processes of saving and restoring the state of the CPU are performed automatically by the SMM hardware in the CPU upon detection of the SMI event. Both the state save process and the SMM handler code are possible only through a grant of read/write access to the SMRAM region.
Memory regions in the High Memory Area (HMA) above the 1 Mbyte boundary (1 MB+(64K-16)) are discounted for use by devices that compete for UMB space since the DOS kernel is located in the UMB when "dos-high" is specified in config.sys. Accordingly, the upper memory block (UMB) space is valuable and advantageously conserved. Operations utilizing memory regions below 640 kbytes are also prohibited since the memory region from 0 to 640 kbytes is reserved for DOS execution. Accordingly, if real mode execution is sought for a particular function, memory addressing is to be constrained to the memory region between 640 kbyte and the 1 Mbyte boundary. Unfortunately, in a typical computer system many resources are mapped into the Upper Memory Blocks from 640 kbyte to 1 Mbyte region.
What is needed is a circuit and operating method that support shared access for multiple resources in the Upper Memory Blocks region of memory in a range of memory addresses from 640 kbyte to 1 Mbyte.